1. Field of the Invention
The present invention relates to a semiconductor memory and a fabrication method of the semiconductor memory. It is particularly related to a miniaturized nonvolatile semiconductor memory encompassing a plurality of memory cell transistors, each of the memory cell transistors being implemented by a gate electrode structure, which encompasses an inter-electrode dielectric sandwiched between a first conductive layer and a second conductive layer. The semiconductor memory encompasses a plurality of cell columns, each of the cell columns embracing serially connected memory cell transistors, and the cell columns being arranged very close to each other.
2. Description of the Related Art
The inter-cell spacing of semiconductor memories is decreasing at approximately a 30% per annum in order to achieve high integration and miniaturization. There are concerns of increasing inter-cell coupling accompanying with adoption of an inter-electrode dielectric having a higher dielectric constant, as an architecture for resolving problems associated with the decrease in inter-cell spacing and its concurrent problems.
Earlier nonvolatile semiconductor memories have been implemented by a polysilicon first conductive layer, which serves as a floating gate electrode. The information of a cell is configured to be stored in the first conductive layer, by retaining electrical charges in the first conductive layer (floating gate electrodes). Therefore, between a ‘written cell’ retaining electrical charges and an ‘erased cell’ not retaining electrical charges in a miniaturized nonvolatile semiconductor memory, a so-called “inter-cell coupling” increases as the inter-cell spacing decreases. Thus, a method of controlling inter-cell coupling by doping device isolation films with fluorine so as to reduce the dielectric constant is proposed, as disclosed in Japanese Patent Application Laid-open No. 2001-15616.
Meanwhile, as a result of decreasing the inter-cell spacing even more than before, increasing the capacitor area by employing a three-dimensional structure that has adopted an ONO film as the inter-electrode dielectric formed between the first conductive layer (floating gate electrodes) and the second conductive layer (control gate electrodes) becomes impossible. The ONO film embraces a triple layer film of a silicon oxide film (SiO2 film), a silicon nitride film (Si3N4 film), and a silicon oxide film (SiO2 film). Thus, in order to implement the miniaturized nonvolatile semiconductor memory, it is necessary to use an insulating film with a higher dielectric constant than before as the inter-electrode dielectric.
Since usage of a high dielectric constant insulating film allows increased capacitance without decreasing the film thickness, there are expectations of no increase in leakage currents and no need of a three-dimensional structure. Furthermore, the fabrication process will become simplified because a three-dimensional structure is no longer necessary, whereby as a result, it is expected that a device with high performance will be fabricated, the fabrication method thereof will be simplified, and implementation of a high yielding fabrication process will be possible.
A structural cross sectional view of a memory cell transistor of an earlier nonvolatile semiconductor memory viewed from a direction perpendicular to bit lines in a stage where up to the inter-electrode dielectric has been stacked is shown in FIG. 1.
As shown in FIG. 1, the memory cell transistor of the earlier nonvolatile semiconductor memory provokes a problem since the inter-cell coupling (C1 in FIG. 1) between the first conductive layers (floating gate electrodes) 3 increases as the inter-cell spacing decreases.
In addition, employment of an inter-electrode dielectric 8e made from a material with a higher dielectric constant than that of silicon oxide causes the electric field arising from accumulated electric charge in the ‘written cell’ to spread to adjacent cells via the inter-electrode dielectric 8e so that the ‘written cell’ capacitively couples to the adjacent cells (see C2 in FIG. 1). In the case where the relative dielectric constant ∈r of the inter-electrode dielectric 8e is higher than that of the silicon oxide film, the inter-cell coupling C2 is greater than C1, so that the problem of the inter-cell coupling C2 is even more serious.
Consequently, in light of the above discussion, although employment of the insulating film with a higher dielectric constant for the inter-electrode dielectric 8e is required, the development of a controlling architecture of inter-cell coupling through the inter-electrode dielectric is necessary for implementing a miniaturized, highly integrated, and highly efficient nonvolatile semiconductor memory. In the controlling architecture of the inter-cell coupling in the miniaturized nonvolatile semiconductor memory, a structure such that the inter-electrode dielectric 8e extends along the length of word lines as shown in FIG. 1 cannot be employed.